Fx1s performance specification project, specification, note Operation Control Mode, I / O Control Method through stored program cycle operation, batch processing method I / O Instruction can refresh operation time when executing END instruction, basic instruction: 0.55 to 0.7 s application instruction: 3.7 to several hundred s programming language, logic ladder diagram and instruction list, use step ladder diagram can generate SFC type program capacity, built-in 2k step EEPROM storage box fx1n-EEPROM-8l number of optional instructions, bASIC SEQUENCE INSTRUCTIONS: 27 Step Ladder Instructions: 2 Application Instructions: 85 maximum available 167 application instructions, including all changed I / O configurations, max Total I / O Auxiliary Relay (M Coil) General 384 point M0 to M383 lock 128 point (subsystem) M384 to M511 special 256 point M8000 to M8255 state relay (s coil) General 128 point S0 to S127 initial 10 point (subsystem) S0 to S9 timer (t)100 MS, range: 0 to 3276.7 s 63 dots T0 to T5510 MS, range: 0 to 327.67 s 31 dots T32 to T621 MS when special m coils are in operation, range: 0.001 to 32.767 s 1 dot T63 counter (C) general, range: 1 to 3276716 points C0 to C15 type: 16-bit increments lock, range: 1 to 3276716 points C16 TO C31 type: 16-bit increments high-speed counter (C) single-phase, range:-2147483648 to + 2147483647 FX0: select up to 4 single-phase counters, combination counter frequency not more than 2 Khz. Fx0s: Frequency and must not be greater than 14 Khz when using multiple single-phase counters. Only single-phase and dual-phase high-speed counters are allowed. When using a two-phase counter, the maximum counting speed must be greater than 14 Khz, calculated as (counting side number 5,2Ph counter speed) + 1ph counter speed. Sentence is too long, please supply a shorter sentence, range: 0 to 2552 points indirectly input D8013 or D8030 & amp; D803114 data special 256 points (including D8030, D8031) from D8000 TO D8255 TYPE: 16-bit Data Store Register addressing 16 point V and Z type: 16-bit Data Store Register Index (P) for CALL 64 point P0 to P64 for Interrupt 6 point 100 * to 130 * (up trigger * 1, down trigger * 0) nesting hierarchy, for Mc and MRC 8 point n 0 to n 7 constant, Decimal K 16 bit:-32768 to + 3276832 bit:-2147483648 to + 2147483647 H 16 bit: 0000 to 32 bit: 000000 to FFFFFFFF

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